Substrate series resistance represents a significant portion of the overall device on-resistance in vertical power devices. Current manufacturing methods accomplish the reduction in substrate series resistance by grinding material off the backside of the wafers after the necessary circuit patterns have been fabricated on the front side of the wafers. The final wafer thickness, however, is limited since continued grinding of material off the backside of the wafer increases the risk that the wafer may crack or break due to the stress created during the thickness-trimming (thinning) process. Moreover, too much material ground off the backside of the wafer increases the risk that the wafer may crack or break during wafer handling. FIG. 1 shows a simplified cross-sectional view of a partial semiconductor wafer 110 having the gate and source electrodes of a vertical power Field Effect Transistor (FET) formed near the front surface 120 of wafer 110 and the drain formed at the rear surface 130 thereof. Where X represents the thickness of the FET device region having source and gate electrodes, and Y represents the thickness of the drain electrode region. If too much thickness Y of rear surface 130 or the bulk silicon is removed, wafer handling becomes nearly impossible.
Even if the wafer survives the wafer thickness-trimming process, the thinned wafer may still be subject to breakage during the die sawing process. During the sawing process, stress may be created in the dicing lane regions. The created stress is a source of crack propagation into integrated circuit regions causing fatal defects.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved method for supporting and handling ultra thin semiconductor wafers that reduces the risk of wafer damage.